1. Field of the Invention
The present invention relates to a wafer edge exposure apparatus and a water edge exposure method. More particularly, the present invention relates to a wafer edge exposure apparatus and wafer edge optical exposing method for accurately exposing the edge of resist coated over a semiconductor wafer.
2. Description of the Background Art
FIG. 3 shows a flowchart representing a popular processing flow to be effected for a certain layer (called here an “ithlayer”) in connection with a related-art semiconductor device manufacturing method. During the processing shown in FIG. 3, resist is applied over a semiconductor wafer by means of a spin coater (step 100).
The resist applied to the edge of the semiconductor water produces foreign substances when interfering with a mechanism of retaining a semiconductor wafer in subsequent processes. In order to prevent production of such foreign substances, the resist applied to the edge of the wafer is removed as much as 1 mm width in the spin coater by means of a thinner (step 102).
Next, the semiconductor wafer is subjected to pattern exposure performed by a stepper (step 104). Through exposure processing, a desired pattern is transferred onto the resist on the semiconductor wafer upon exposed to radiation.
The semiconductor wafer is further subjected to edge exposure processing performed by an edge exposure apparatus (step 106). The edge exposure apparatus is for exposing the edge of a wafer over a desired width (e.g., 2 mm or 3 mm).
When having finished undergoing the pattern exposure processing and edge exposure processing, the semiconductor wafer is subjected to process of developing a resist (step 108). As a result of the processing being performed, the resist located along the edge of the wafer is removed over a desired width (2 mm or 3 mm), and the resist on the semiconductor wafer is patterned into a desired pattern.
There is then performed processing for etching the semiconductor wafer while the thus-patterned resist is taken as a mask or implanting impurities into the semiconductor wafer (step 110).
FIG. 4A is a plan view showing a semiconductor wafer to be processed through a round of processing operations set forth. FIG. 4B is a cross-sectional view of the semiconductor wafer. More specifically, FIG. 4A is a plan view showing a semiconductor wafer 10 having finished undergoing processing pertaining to step 102; that is, when resist 12 has been removed from the edge of the wafer by means of a thinner. FIG. 4B is a cross-sectional view of the semiconductor wafer 10 taken along line A—A shown in FIG. 4A. As shown in FIG. 4B, when the resist 12 is removed from the edge of the wafer by means of the thinner, the end surface of the resist 12 is tapered. Here, the following description is based on the assumption that the resist 12 is applied over a first layer film 14, as shown in FIG. 41.
FIG. 5 shows the first layer film 14 when the film has been etched while the resist 12 shown in FIG. 4B is taken as a mask. When the end face of the resist 12 is tapered as shown in FIG. 4B, the outer most edge of the resist 12 does not sufficiently act as a mask during the course of etching operation. Hence, when such a resist 12 is used as a mask, the vicinity of the end face of the first layer film 14 is etched insufficiently, as shown in FIG. 5. As a result, foreign obstacles become apt to arise.
FIG. 6A is a plan view of the semiconductor wafer 10 after having finished undergoing processing pertaining to step 108; that is, after the resist 12 has been removed from the edge of the wafer through edge exposure processing and development processing. FIG. 6B is a cross-sectional view of the semiconductor wafer 10 when taken along line A—A shown in FIG. 6A.
As shown in FIG. 6B, the edge of the resist 12 can be removed such that the end face of the resist 12 becomes substantially perpendicular, through edge exposure processing and development processing. When such a resist 12 is used as a mask, the first layer film 14 can be etched to an appropriate state; namely, a state in which foreign substances are less likely to be generated. Hence, the related-art manufacturing method enables appropriate processing of the ith layer of a semiconductor device.
However, during the course of manufacture of a semiconductor device, a plurality of layers must be formed on the semiconductor wafer 10. For example, FIG. 8 shows a state in which a first layer film 16, a second layer film 18, a third layer film 20, a fourth layer film 22, and a fifth layer film 24 are formed on the semiconductor wafer 10 and the resist 12 is coated on the first through fifth layer films. In this case, there arises a necessity for exposing the edge of the resist 12 at a position situated above the fifth layer film 24, thereby removing the edge.
The related-art edge exposure apparatus to be used for exposing the edge of the resist 12 is configured such that a focal point of the exposure apparatus is substantially accords with the surface position of the semiconductor wafer 10. Therefore, when the resist 12 is formed on the fifth layer film 24, the focal point of exposure light originating from the edge exposure apparatus comes out of accordance with the location of the resist 12.
FIG. 9 shows a state of the semiconductor wafer when the wafer has finished undergoing development processing while the focal point of the exposure light remains out of accordance with the surface position of the resist 12. In this case, the edge of the resist 12 is not activated properly, and hence the end face of the resist 12 is slightly tapered. If the end face of the resist 12 is tapered, the fifth layer 24 becomes apt to generate foreign substance after etching processing, as in the case shown in FIG. 5. In this respect, the related art manufacturing method has failed to completely solve a problem of foreign substances arising from an edge of a film to be etched.